Current integrated circuit (IC) design is largely dedicated to large systems integrating software and hardware to perform multiple tasks simultaneously, or almost simultaneously. Some of these designs include system on a chip (SoC) configurations, typically designed to execute different applications that compete for system resources (e.g., memory, processor time, and bus bandwidth). Due to a large number of operating parameters to consider, system designers typically explore obvious extreme parameter corners that may render inefficient design architectures having inefficient performance, or leading the system designer to an unwarranted conclusion about the design. Moreover, some combinations of parameter values may be overlooked, resulting in system flaws that may be unrecoverable in certain situations. Also, in some situations it may be desirable for a designer to perform a “what if” analysis, in which input parameters are constrained to pre-selected values to determine what is the outcome in SoC performance. In such circumstances, it is desirable to have a tool that systematically and exhaustively explores the parameter space to find areas with an increased likelihood to find flaws in the design, and to reduce the computational time it takes to find these parameter space areas.
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